1. Field of the Invention
The present invention relates to a method and a device for the digital synthesis of a clock signal.
It applies to the making of clock signal generators for radio communications and, especially, to the construction of frequency hopping transmission systems where the frequency changes very swiftly in time by successive stages.
In systems of this type, the clock signals may be used as such or they may be copied by means of phase-lock loops to improve the remote noise characteristics through the filtering effect exerted by the loops. More generally, they can be used as reference clocks in one of the loops of a frequency synthesizer using a digital comparator of the phase/frequency type, for example in an addition loop, in order to enable its transposition in any range of frequencies.
In addition to the fact that these generators must have sound spectral quality while at the same time being capable of undergoing phase and frequency modulation, their use in terrestrial equipment or spacecraft, for example, means that they should consume little power and should occupy the smallest possible volume.
2. Description of the Prior Art
One known approach, which possesses the above characteristics to a great extent, lies in making a frequency synthesizer which entirely or partially consists of a direct digital synthesizer, namely a synthesizer that includes no phase-locking loop. According to this approach, the digital synthesizer is organized around an accumulating circuit or a sequential digital circuit, the content of which is increased by a determined quantity at each pulse of a signal given by a local clock. This circuit usually has an adder, the output of which is connected to a locking register controlled by a clock signal. The output of the locking register is looped to one of the inputs of the adder and the other input is the input of the accumulator. In a great many applications, and especially in those to which the invention relates, the accumulator is also called a "phase accumulator" because, in this case, the digital term /P, which is applied to its input constitutes a phase increment by one clock unit T.sub.c of the output signal. This term determines the speed of variation of the phase in time, namely, its frequency. The number of bits that can be memorized in the accumulator defines the capacity N of this accumulator. This capacity is equal to M=2.sup.N for binary encoding. Thus the adding operation performed at each clock signal front may be considered to be a modulo M adding operation of the type that verifies a relationship of the following form: EQU P.sub.K =K..DELTA.P mod M
(with 0.ltoreq..DELTA.P&lt;M
where K is the number of computation clock periods T.sub.c and P.sub.K is the binary number obtained at the output of the accumulator at the instant t.sub.K =K.T.sub.c
When the quantity K..DELTA.P is greater than or equal to M, a carry-over signal R.sub.K appears at the output of the adder for a time equal to the period T.sub.c of the clock signal. P.sub.K is then written at the overflow instant: EQU PK=M-K..DELTA.P&lt;.DELTA.P and R.sub.K =1
In principle, the value M corresponds exactly to a phase of 2.pi. radians. Whenever there is an overflow of the accumulator, there is therefore a rotation of 2n radians, and the periodicity T.sub.s of the overflows verifies relationships of the following form: EQU Ts=(M/.DELTA.P).T.sub.c
where F.sub.s =(.DELTA.P/M).F.sub.c =.sub.T.sbsb.s.sup.1
However, these relationships are not totally verified unless the remainder of the Euclidian division of M by .DELTA.P is nil and this is true only on an average in the other cases. For when M cannot be divided by .DELTA.P, the time T'.sub.s that elapses between two successive overflows is always a whole multiple of a clock period T.sub.c and fluctuates by one unit of T.sub.c. This defines the degree of temporal precision with which the clock period T.sub.s can be obtained. Naturally, to increase the precision of the clock period T.sub.s, the computation clock period T.sub.c must be reduced, but this approach quickly becomes impracticable because of the technological limitations of digital integrated circuits. Finally, a clock synthesized in this way always has a positional modulation of its rising edge in time. This may be represented in terms of a phase fluctuation or unwanted phase modulation with a peak-to-peak amplitude having a period of T.sub.c reduced to the period of the synthesized signal T.sub.s. The modulation index m is then: EQU m=(1/2).(T.sub.c /T.sub.s).2.pi.
For example, if .pi. is smaller than 0.3, the amplitudes of the unwanted lines obtained are given with good approximation by a first order Bessel function J.sub.1 (m), that is m/2.
One procedure, enabling a substantial reduction in the phase fluctuation, is known from the French patent application No. FR 85 19067, filed on behalf of the Applicant and entitled "High Frequency Digital Synthesizer with Non-Periodic Correction Optimizing Spectral Speed". According to this approach, the accumulator is made, like a systolic system, so as to work at the highest possible frequency, and a temporal analog interpolation of the position of the output signal front is computed. This output is initialized by the instant at which a voltage gradient, triggered by the overflow of the accumulator, coincides with the output voltage of a digital/analog converter controlled by a time error datum resulting from prior computation. However, this approach requires the use of fast analog circuits in which the linearity is vital in order to obtain good results. This entails settings which complicate the use of this method.